1. Field of the Invention
The present invention relates to a soft output Viterbi algorithm (SOVA) decoder and a method of performing SOVA decoding.
2. Background of the Invention
Convolutional encoders are types of encoders that generate a symbol to be transmitted based on a current state determined using one or more previous input values. Such encoders are generally implemented by a finite state machine.
Decoding a received signal originating from a convolutional encoder involves finding the most probable sequence of emitted data, based on the information received from the transmission channel.
A soft-decision output Viterbi algorithm (SOVA) has been proposed, which uses the log-likelihood ratios (LLR) generated based on the received symbols to generate, in parallel to the decoded data, an indication of the reliability of the decoded data.
SOVA decoders generally comprise a survivors memory unit (SMU) formed of a series of multiplexer stages each comprising multiplexers for each state and used to perform a trace back algorithm on values determined by a number L of previous symbols. The SMU thereby evaluates multiple sequences of state transitions, and by switching the multiplexers based on the most likely paths, reduces these paths to a single survivor path, which indicates the decoded data as a hard decision value after a delay of L symbols.
A reliability memory unit (RMU), formed of a series of logic stages, operates in parallel to the SMU, and processes path metric differences (PMDs) based on the most probable paths determined by the SMU. The PMDs are determined based on the LLR values, and indicate the difference in probabilities between two paths. Each of the logic stages comprises a logic unit for each state, and the PMD values are propagated through these logic units based on hard decisions from the SMU, in order to determine reliability values for the survivor paths.
A problem of SOVA decoders is that they are relatively complex to implement and costly in terms of hardware resources. In particular, to recover a sequence based on symbols of S bits generated by a convolutional encoder of NS states, the number of states NS is generally a power of 2, NS×2S, a state corresponding to each symbol, and 8S paths are evaluated, because from each state, there are generally two possible state transitions. The data to reduce these paths needs to be stored and evaluated. In particular, each of the logic units of each stage of the RMU comprises a buffer for storing the generated reliability values for one symbol period. Assuming that there are L stages and that each stage comprises NS logic units, there would be NS×L logic units, each having a memory capable of storing one multiple-bit reliability value. The memory used by these logic units can be high.